The present invention relates to a field programmable gate array (hereinafter referred to as an FPGA), and more particularly, to an FPGA for which a magnetic storage device is used.
Recently, as techniques for the fine structure of semiconductor devices have been developed and the manufacturing processes have become complicated, masks and manufacturing costs for ASICs (Application Specific Integrated Circuits), which are logic integrated circuits, have increased. Therefore, the cost of manufacturing ASICs can not be offset unless they can be mass produced. Thus, FPGAs are exploited, rather than ASICs, when only a small number of a specific type of logic circuits is required, or when a specific logic circuit is to be used as a prototype.
Conventionally, an FPGA is a large integrated circuit that can be used to create a user-designed arbitrary logic circuit. While on the one hand, to obtain a new ASIC an order for its manufacture must be placed with a maker, and the function of the ASIC that is thus obtained can not thereafter be changed, on the contrary, since the function of a new logic circuit design can be written to and implemented using a conventional FPGA, a user need not order a new integrated circuit from a maker; the user may prepare a working copy of the new logic circuit merely by changing the functional design of an FPGA.
FIG. 6 is a functional block diagram showing the overall configuration of a conventional FPGA. In FIG. 6, an FPGA 4 includes a static random access memory (hereinafter referred to as an SRAM), multiple logic blocks 5 and multiple switching circuits 6.
The logic blocks 5 are programmable logic circuits, and include at least one latch circuit, or two or more (not shown). The latch circuit stores logic structure information for defining the logic structure of the logic block 5. The SRAM 3 stores connection information for the interconnection of the logic blocks 5. And the switching circuits 6 are connected between the logic blocks 5, and are turned on or off in accordance with the connection information stored in the SRAM 3. With this configuration, the logic blocks 5 are mutually connected or disconnected.
A flash memory 2, which is a nonvolatile semiconductor storage device, is also provided on a card 1 whereon the FPGA 4 is mounted. The connection information and the logic structure information are included in a user prepared program that is stored in the flash memory 2, and when the power is switched on, the connection information is transferred from the flash memory 2 to the SRAM 3. Based on this connection information, which is transferred from the flash memory 2 and stored in the SRAM 3, the switching circuits 6 of the FPGA 4 are turned on or off. Further, after the power is switched on, the logic structure information is transmitted directly from the flash memory 2 to the logic blocks 5, where it is stored. As a result, the logic structure desired by the user can be provided. Furthermore, the user can freely alter the FPGA logic circuit by changing the connection information and the logic structure information that is stored in the flash memory 2.
The manufacturing process technology of the flash memory differs greatly from that of the circuits in the FPGA 4, and the required voltage is higher than that required by the circuit device of the FPGA 4. Therefore, mounting the flash memory 2 and the FPGA 4 on the same chip is difficult, and instead of the flash memory 2, the SRAM 3 and the FPGA 4 being formed on the same chip, the flash memory 2 is formed on a separate chip. However, since the SRAM 3 is a volatile semiconductor storage device, conventionally, the connection information must be read from the external FPGA 4 each time the power is switched on, and is then transferred to the internal SRAM 3. Thus, it takes a long time until the FPGA 4 becomes ready for operations after power is turned on.
Furthermore, since the flash memory 2 and the FPGA 4 are mounted on different chips, and since multiple connecting lines are required to transmit the connection information from the flash memory 2 to the SRAM 3, the size of the card 1 is increased.
Further, to partially change a program held by the flash memory 2, all the stored data must be erased and the changed program rewritten. Therefore, in order to change part of the connection information or the logic structure information, the rewriting of data also takes a long time.